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to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation ( http://www.renesas.com ) send any inquiries to http://www.renesas.com/inquiry .
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rev.2.00 aug 27, 2008 page 1 of 41 rej03b0120-0200 r8c/20 group, r8c/21 group renesas mcu 1. overview this mcu is built using the high-perfo rmance silicon gate cmos process us ing the r8c cpu core and is packaged in a 48-pin plastic molded lqfp. this mcu operates using sophisticated in structions featuring a high level of instruction efficiency. with 1 mbyte of address space, it is capable of executi ng instructions at high speed. this furthermore, the data flash (1 kb x 2 blocks) is embedded in the r8c/21 group. the difference between r8c/20 and r8c/21 groups is only th e existence of the data flas h. their peripheral functions are the same. 1.1 applications automotive, etc. rej03b0120-0200 rev.2.00 aug 27, 2008
r8c/20 group, r8c/21 group 1. overview rev.2.00 aug 27, 2008 page 2 of 41 rej03b0120-0200 1.2 performance overview table 1.1 outlines the functions and specifications for r8c/20 group and ta ble 1.2 outlines the functions and specifications for r8c/21 group. notes: 1. when using options, be sure to inquire about the specification. 2. i 2 c bus is a registered trademark of koninklijke philips electronics n.v. table 1.1 functions and specifications for r8c/20 group item specification cpu number of fundamental in structions 89 instructions minimum instruction execution time 50 ns (f(xin) = 20 mhz, vcc = 3.0 to 5.5 v) 100 ns (f(xin) = 10 mhz, vcc = 2.7 to 5.5 v) operating mode single-chip address space 1 mbyte memory capacity refer to table 1.3 product information for r8c/20 group peripheral function ports i/o ports: 41 pins, input port: 3 pins timers timer ra: 8 bits x 1 channel, timer rb: 8 bits x 1 channel (each timer equipped with 8-bit prescaler) timer rd: 16 bits x 2 channel (circuits of input capture and output compare) timer re: with comp are match function serial interface 1 channel (uart0) clock synchronous i/o, uart 1 channel (uart1) uart clock synchronous serial interface 1 channel i 2 c bus interface (2) , clock synchronous seri al i/o with chip select lin module hardware lin: 1 channel (timer ra, uart0) a/d converter 10-bit a/d conv erter: 1 circuit, 12 channels watchdog timer 15 bits x 1 channel (with prescaler) reset start selectable interrupt internal: 11 sources, extern al: 5 sources, software: 4 sources, priority level: 7 levels clock generation circuits 2 circuits xin clock generation circuit (with on-chip feedback resistor) on-chip oscillator (high speed, low speed) high-speed on-chip oscillator has frequency adjustment function. oscillation stop detection function stop detection of xin clock oscillation voltage detection circuit on-chip power-on reset circuit include on-chip electric characteristics supply voltage vcc = 3.0 to 5.5 v (f(xin) = 20 mhz)(j version) vcc = 3.0 to 5.5 v (f(xin) = 16 mhz)(k version) vcc = 2.7 to 5.5 v (f(xin) = 10 mhz) current consumption typ. 11.0 ma (vcc = 5 v, f(xin) = 20 mhz, high-speed on- chip oscillator stopping) typ. 5.3 ma (vcc = 5 v, f(xin) = 10 mhz, high-speed on-chip oscillator stopping) flash memory programming and erasure voltage vcc = 2.7 to 5.5 v programming and erasure endurance 100 times operating ambient temperature -40 to 85 c -40 to 125 c (option (1) ) package 48-pin mold-plastic lqfp
r8c/20 group, r8c/21 group 1. overview rev.2.00 aug 27, 2008 page 3 of 41 rej03b0120-0200 notes: 1. when using options, be sure to inquire about the specification. 2. i 2 c bus is a registered trademark of koninklijke philips electronics n.v. table 1.2 functions and specifications for r8c/21 group item specification cpu number of fundamental in structions 89 instructions minimum instruction execution time 50 ns (f(xin) = 20 mhz, vcc = 3.0 to 5.5 v) 100 ns (f(xin) = 10 mhz, vcc = 2.7 to 5.5 v) operating mode single-chip address space 1 mbyte memory capacity refer to table 1.4 product information for r8c/21 group peripheral function ports i/o ports: 41 pins, input port: 3 pins timers timer ra: 8 bits x 1 channel, timer rb: 8 bits x 1 channel (each timer equipped with 8-bit prescaler) timer rd: 16 bits x 2 channel (circuits of input capture and output compare) timer re: with compare match function serial interface 1 channel (uart0) clock synchronous i/o, uart 1 channel (uart1) uart clock synchronous serial interface 1 channel i 2 c bus interface (2) , clock synchronous serial i/o with chip select lin module hardware lin: 1 channel (timer ra, uart0) a/d converter 10-bit a/d converter: 1 circuit, 12 channels watchdog timer 15 bits x 1 channel (with prescaler) reset start selectable interrupts internal: 11 sources, external: 5 sources, software: 4 sources, priority level: 7 levels clock generation circuits 2 circuits xin clock generation circuit (with on-chip feedback resistor) on-chip oscillator (high speed, low speed) high-speed on-chip oscillator has frequency adjustment function. oscillation stop detection function stop detection of xin clock oscillation voltage detection circuit on-chip power-on reset circ uit include on-chip electric characteristics supply voltage vcc = 3.0 to 5.5 v (f(xin) = 20 mhz)(j version) vcc = 3.0 to 5.5 v (f(xin ) = 16 mhz)(k version) vcc = 2.7 to 5.5 v (f(xin) = 10 mhz) current consumption typ. 11.0 ma (vcc = 5 v, f(xin) = 20 mhz, high-speed on- chip oscillator stopping) typ. 5.3 ma (vcc = 5 v, f(xin) = 10 mhz, high-speed on-chip oscillator stopping) flash memory programming and erasure voltage vcc = 2.7 to 5.5 v programming and erasure endurance 10,000 times (data flash) 1,000 times (program rom) operating ambient temperature -40 to 85 c -40 to 125 c (option (1) ) package 48-pin mold-plastic lqfp
r8c/20 group, r8c/21 group 1. overview rev.2.00 aug 27, 2008 page 4 of 41 rej03b0120-0200 1.3 block diagram figure 1.1 shows a block diagram. figure 1.1 block diagram r8c cpu core timer timer ra (8 bits) timer rb (8 bits) timer rd (16 bits 2 channels ) timer re (8 bits) a/d converter (10 bits 12 channels) system clock generation circuit xin-xout high-speed on-chip oscillator low-speed on-chip oscillator uart or clock synchronous serial i/o (8 bits 1 channel) memory watchdog timer (15 bits) rom (1) ram (2) multiplier r0h r0l r1h r2 r3 r1l a0 a1 fb sb usp isp intb pc flg i/o port notes: 1. rom size depends on mcu type. 2. ram size depends on mcu type. i 2 c bus interface or clock synchronous serial i/o with chip select (8 bits 1 channel) 8 port p1 6 port p3 3 3 port p4 8 port p0 8 port p2 8 port p6 uart (8 bits 1 channel) lin module (1 channel)
r8c/20 group, r8c/21 group 1. overview rev.2.00 aug 27, 2008 page 5 of 41 rej03b0120-0200 1.4 product information table 1.3 lists product information for r8c/20 group an d table 1.4 lists product information for r8c/21 group. note: 1. do not use addresses 20000h to 23fffh because t hese areas are used for the emulator debugger. refer to 23. notes on emulator debugger of hardware manual. figure 1.2 type number, memory size, and package of r8c/20 group table 1.3 product information for r8c/20 group current of aug. 2008 type no. rom capacity ram capacity package type remarks r5f21206jfp 32 kbytes 2 kbytes plqp0048kb-a j version flash memory version r5f21207jfp 48 kbytes 2.5 kbytes plqp0048kb-a r5f21208jfp 64 kbytes 3 kbytes plqp0048kb-a r5f2120ajfp 96 kbytes 5 kbytes plqp0048kb-a r5f2120cjfp 128 kbytes (1) 6 kbytes plqp0048kb-a r5f21206kfp 32 kbytes 2 kbytes plqp0048kb-a k version r5f21207kfp 48 kbytes 2.5 kbytes plqp0048kb-a r5f21208kfp 64 kbytes 3 kbytes plqp0048kb-a r5f2120akfp 96 kbytes 5 kbytes plqp0048kb-a r5f2120ckfp 128 kbytes (1) 6 kbytes plqp0048kb-a part number r 5 f 21 20 6 j xxx fp package type: fp: plqp0048kb-a (0.5 mm pin-pitch, 7 mm square body) rom number classification j: operating ambient temperature -40c to 85c (j version) k: operating ambient temperature -40c to 125c (k version) rom capacity 6: 32 kb 7: 48 kb 8: 64 kb a: 96 kb c: 128 kb r8c/20 group r8c/2x series memory type f: flash memory version renesas mcu renesas semiconductors
r8c/20 group, r8c/21 group 1. overview rev.2.00 aug 27, 2008 page 6 of 41 rej03b0120-0200 note: 1. do not use addresses 20000h to 23fffh because t hese areas are used for the emulator debugger. refer to 23. notes on emulator debugger of hardware manual. figure 1.3 type number, memory size, and package of r8c/21 group table 1.4 product information for r8c/21 group current of aug. 2008 type no. rom capacity ram capacity package type remarks program rom data flash r5f21216jfp 32 kbytes 1 kbyte x 2 2 kbytes plqp0048kb-a j version flash memory version r5f21217jfp 48 kbytes 1 kbyte x 2 2.5 kbytes plqp0048kb-a r5f21218jfp 64 kbytes 1 kbyte x 2 3 kbytes plqp0048kb-a R5F2121AJFP 96 kbytes 1 kbyte x 2 5 kbytes plqp0048kb-a r5f2121cjfp 128 kbytes (1) 1 kbyte x 2 6 kbytes plqp0048kb-a r5f21216kfp 32 kbytes 1 kbyte x 2 2 kbytes plqp0048kb-a k version r5f21217kfp 48 kbytes 1 kbyte x 2 2.5 kbytes plqp0048kb-a r5f21218kfp 64 kbytes 1 kbyte x 2 3 kbytes plqp0048kb-a r5f2121akfp 96 kbytes 1 kbyte x 2 5 kbytes plqp0048kb-a r5f2121ckfp 128 kbytes (1) 1 kbyte x 2 6 kbytes plqp0048kb-a part number r 5 f 21 21 6 j xxx fp package type: fp: plqp0048kb-a (0.5 mm pin-pitch, 7 mm square body) rom number classification j: operating ambient temperature -40c to 85c (j version) k: operating ambient temperature -40c to 125c (k version) rom capacity 6: 32 kb 7: 48 kb 8: 64 kb a: 96 kb c: 128 kb r8c/21 group r8c/2x series memory type f: flash memory version renesas mcu renesas semiconductors
r8c/20 group, r8c/21 group 1. overview rev.2.00 aug 27, 2008 page 7 of 41 rej03b0120-0200 1.5 pin assignments figure 1.4 shows pin assignments (top view). figure 1.4 pin assignments (top view) 48 p3_7/sso 47 p0_0/an7 46 p0_1/an6 45 p0_2/an5 44 p0_3/an4 43 p6_1 42 p6_2 41 p6_0/treo 40 p4_2/vref 39 p0_4/an3 38 p0_5/an2 37 p0_6/an1 13 14 15 16 17 18 19 20 21 22 23 24 p2_6/trdioc1 p2_5/trdiob1 p2_4/trdioa1 p2_3/trdiod0 p2_2/trdioc0 p2_1/trdiob0 p2_0/trdioa0/trdclk p1_7/traio/int1 p1_6/clk0 p1_5/rxd0/(traio)/(int1) (2) p1_4/txd0 p1_3/ki3/an11 12 p2_7/trdiod1 11 vcc/avcc 10 p4_6/xin 9 vss/avss 8 (1) p4_7/xout 7 reset 6 p4_4 5 p4_3 4 mode 3 p3_4/sda/scs 2 p3_3/ssi 1 p3_5/scl/ssck 25 26 27 28 29 30 31 32 33 34 35 36 p4_5/int0 p6_6/int2/txd1 p6_7/int3/rxd1 p1_2/ki2/an10 p1_1/ki1/an9 p1_0/ki0/an8 p3_1/trbo p3_0/trao p6_5 p6_4 p6_3 p0_7/an0 pin assignments (top view) package: plqp0048kb-a 0.5 mm pin pitch, 7 mm square body r8c/20 group, r8c/21 group notes: 1. p4_7 is an input-only port. 2. can be assigned to the pin in parentheses by a program. 3. confirm the pin 1 position on the package by referring to the package dimensions.
r8c/20 group, r8c/21 group 1. overview rev.2.00 aug 27, 2008 page 8 of 41 rej03b0120-0200 1.6 pin functions table 1.5 lists the pin functions and table 1.6 lists the pin name information by pin number. i: input o: output i/ o: input and output table 1.5 pin functions type symbol i/o type description power supply input vcc vss i apply 2.7 v to 5.5 v to the vcc pin. apply 0 v to the vss pin. analog power supply input avcc, avss i applies the power supply for the a/d converter. connect a capacitor between avcc and avss. reset input reset i input ?l? on this pin resets the mcu. mode mode i connect this pin to vcc via a resistor. xin clock input xin i these pins are provided for the xin clock generation circuit i/o. connect a ceramic resonator or a crystal oscillator between the xin and xout pins. to use an externally derived clock, input it to the xin pin and leave the xout pin open. xin clock output xout o int interrupt input int0 to int3 iint interrupt input pins. int0 timer rd input pins. int1 timer ra input pins. key input interrupt ki0 to ki3 i key input interrupt input pins. timer ra traio i/o timer ra i/o pin. trao o timer ra output pin. timer rb trbo o timer rb output pin. timer rd trdioa0, trdioa1, trdiob0, trdiob1, trdioc0, trdioc1, trdiod0, trdiod1 i/o timer rd i/o ports. trdclk i external clock input pin. timer re treo o divided clock output pin. serial interface clk0 i/o transfer clock i/o pin. rxd0, rxd1 i serial data input pins. txd0, txd1 o serial data output pins. i 2 c bus interface scl i/o clock i/o pin. sda i/o data i/o pin. clock synchronous serial i/o with chip select ssi i/o data i/o pin. scs i/o chip-select signal i/o pin. ssck i/o clock i/o pin. sso i/o data i/o pin. reference voltage input vref i reference voltage input pin to a/d converter. a/d converter an0 to an11 i analog input pins to a/d converter. i/o port p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0, p3_1, p3_3 to p3_5, p3_7, p4_3 to p4_5, p6_0 to p6_7 i/o cmos i/o ports. each port contains an input/output select direction register, allowing each pin in that port to be directed for input or output individually. any port set to input can select whether to use a pull-up resistor or not by a program. input port p4_2, p4_6, p4_7 i input only ports.
r8c/20 group, r8c/21 group 1. overview rev.2.00 aug 27, 2008 page 9 of 41 rej03b0120-0200 note: 1. can be assigned to the pin in parentheses by a program. table 1.6 pin name information by pin number pin number control pin port i/o pin functions for of peripheral modules interrupt timer serial interface clock synchronous serial i/o with chip select i 2 c bus interface a/d converter 1 p3_5 ssck scl 2 p3_3 ssi 3p3_4 scs sda 4mode 5p4_3 6p4_4 7 reset 8xoutp4_7 9 vss/avss 10 xin p4_6 11 vcc/avcc 12 p2_7 trdiod1 13 p2_6 trdioc1 14 p2_5 trdiob1 15 p2_4 trdioa1 16 p2_3 trdiod0 17 p2_2 trdioc0 18 p2_1 trdiob0 19 p2_0 trdioa0/trdclk 20 p1_7 int1 traio 21 p1_6 clk0 22 p1_5 (int1 ) (1) (traio) (1) rxd0 23 p1_4 txd0 24 p1_3 ki3 an11 25 p4_5 int0 int0 26 p6_6 int2 txd1 27 p6_7 int3 rxd1 28 p1_2 ki2 an10 29 p1_1 ki1 an9 30 p1_0 ki0 an8 31 p3_1 trbo 32 p3_0 trao 33 p6_5 34 p6_4 35 p6_3 36 p0_7 an0 37 p0_6 an1 38 p0_5 an2 39 p0_4 an3 40 vref p4_2 41 p6_0 treo 42 p6_2 43 p6_1 44 p0_3 an4 45 p0_2 an5 46 p0_1 an6 47 p0_0 an7 48 p3_7 sso
r8c/20 group, r8c/21 group 2. central processing unit (cpu) rev.2.00 aug 27, 2008 page 10 of 41 rej03b0120-0200 2. central processi ng unit (cpu) figure 2.1 shows the cpu registers. the cpu contains 13 registers. of these, r0 , r1, r2, r3, a0, a1, and fb comprise a register bank. two sets of register banks are provided. figure 2.1 cpu registers r2 b31 b15 b8b7 b0 data registers (1) address registers (1) r3 r0h (high-order of r0) r2 r3 a0 a1 intbh b15 b19 b0 intbl fb frame base registers (1) the 4-high order bits of intb are intbh and the 16-low order bits of intb are intbl. interrupt table register b19 b0 usp program counter isp sb user stack pointer interrupt stack pointer static base register pc flg flag register carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved area processor interrupt priority level reserved area c ipl d z s b o i u b15 b0 b15 b0 b15 b0 b8 b7 note: 1. a register bank comprises these registers. two sets of register banks are provided. r0l (low-order of r0) r1h (high-order of r1) r1l (low-order of r1)
r8c/20 group, r8c/21 group 2. central processing unit (cpu) rev.2.00 aug 27, 2008 page 11 of 41 rej03b0120-0200 2.1 data registers (r 0, r1, r2 and r3) r0 is a 16-bit register for transfer, arithmetic, and logic operations. the same applies to r1 to r3. r0 can be split into high-order bit (r0h) and low-order bit (r0l) to be used separately as 8-bit data registers. the same applies to r1h and r1l as r0h and r0l. r2 can be combined with r0 to be used as a 32-bit data register (r2r0). the same applies r3r1 as r2r0. 2.2 address registers (a0 and a1) a0 is a 16-bit register for address register indirect a ddressing and address register relative addressing. they also are used for transfer, arithmetic and logic operations. the same applies to a1 as a0. a1 can be combined with a0 to be used a 32-bit address register (a1a0). 2.3 frame base register (fb) fb is a 16-bit register for fb relative addressing. 2.4 interrupt table register (intb) intb, a 20-bit register, indicates the star t address of an interrupt vector table. 2.5 program counter (pc) pc, 20 bits wide, indicates the addre ss of an instruction to be executed. 2.6 user stack pointer (usp) a nd interrupt stack pointer (isp) the stack pointer (sp), usp and isp, are 16 bits wide each. the u flag of flg is used to switch between usp and isp. 2.7 static base register (sb) sb is a 16-bit register for sb relative addressing. 2.8 flag register (flg) flg is a 11-bit register indicating the cpu status. 2.8.1 carry flag (c) the c flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic and logic unit. 2.8.2 debug flag (d) the d flag is for debug only. set to 0. 2.8.3 zero flag (z) the z flag is set to 1 when an arithmetic operation resulted in 0; otherwise, 0. 2.8.4 sign flag (s) the s flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, 0. 2.8.5 register bank select flag (b) the register bank 0 is selected when the b flag is 0. the register bank 1 is selected when this flag is set to 1. 2.8.6 overflow flag (o) the o flag is set to 1 when the operati on resulted in an overflow; otherwise, 0.
r8c/20 group, r8c/21 group 2. central processing unit (cpu) rev.2.00 aug 27, 2008 page 12 of 41 rej03b0120-0200 2.8.7 interrupt enable flag (i) the i flag enables a maskable interrupt. an interrupt is disabled when the i flag is set to 0, and ar e enabled when the i flag is set to 1. the i flag is set to 0 when an interrupt request is acknowledged. 2.8.8 stack pointer select flag (u) isp is selected when the u flag is set to 0; usp is selected when the u flag is set to 1. the u flag is set to 0 when a hard ware interrupt request is acknowledge d or the int instruction of software interrupt numbers. 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7. if a requested interrupt has greater prior ity than ipl, the interrupt is enabled. 2.8.10 reserved bit if necessary, set to 0. when read, the content is undefined.
r8c/20 group, r8c/21 group 3. memory rev.2.00 aug 27, 2008 page 13 of 41 rej03b0120-0200 3. memory 3.1 r8c/20 group figure 3.1 shows a memory map of r8c/20 group. the r8c/20 group has 1 mbyte of address space from address 00000h to fffffh. the internal rom is allocated lower addresses, beginning with address 0ffffh. for example, a 48-kbyte internal rom is allocated addresses 04000h to 0ffffh. the fixed interrupt vector table is al located addresses 0ffdch to 0ffffh. they store th e starting address of each interrupt routine. the internal ram is allocated higher addresses, beginning with address 00400h. for example, a 2.5-kbyte internal ram is allocated addresses 00400h to 00dffh. th e internal ram is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged. special function registers (sfr) are allocated addr esses 00000h to 002ffh. the peripheral function control registers are allocated here. all addr esses within the sfr, which have noth ing allocated are reserved for future user and cannot be accessed by users. figure 3.1 memory map of r8c/20 group undefined instruction overflow brk instruction address match single step watchdog timer?oscillation stop detection?voltage detection address break (reserved) reset fffffh 0ffffh 0yyyyh 0xxxxh 00400h 002ffh 00000h internal rom (program rom) internal ram sfr (refer to 4. special function registers (sfrs) ) 0ffffh 0ffdch notes: 1. the blank regions are reserved. do not access locations in these regions. 2. do not use addresses 20000h to 23fffh because these areas are used for the emulator debugger. refer to 23. notes on emulator debugger of hardware manual. reserved area 01300h 02000h internal rom (2) (program rom) part number internal rom size address 0yyyyh address zzzzzh r5f21206jfp, r5f21206kfp r5f21207jfp, r5f21207kfp r5f21208jfp, r5f21208kfp r5f2120ajfp, r5f2120akfp r5f2120cjfp, r5f2120ckfp 32 kbytes 48 kbytes 64 kbytes 96 kbytes 128 kbytes 08000h 04000h 04000h 04000h 04000h - - 13fffh 1bfffh 23fffh internal ram address 0xxxxh 00bffh 00dffh 00fffh 00fffh 00fffh 2 kbytes 2.5 kbytes 3 kbytes 5 kbytes 6 kbytes size zzzzzh internal ram 03000h 0ssssh address 0ssssh - - - 037ffh 03bffh
r8c/20 group, r8c/21 group 3. memory rev.2.00 aug 27, 2008 page 14 of 41 rej03b0120-0200 3.2 r8c/21 group figure 3.2 shows a memory map of r8c/21 group. the r8c/21 group has 1 mbyte of address space from address 00000h to fffffh. the internal rom (program rom) is allocated lower addresses, beginning with address 0ffffh . for example, a 48-kbyte internal rom is allocated addresses 04000h to 0ffffh. the fixed interrupt vector table is al located addresses 0ffdch to 0ffffh. they store th e starting address of each interrupt routine. the internal rom (data flash) is allocated addresses 02400h to 02bffh. the internal ram is allocated higher addresses, beginning with address 00400h. for example, a 2.5-kbyte internal ram is allocated addresses 00400h to 00dffh. th e internal ram is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged. special function registers (sfr) are allocated addr esses 00000h to 002ffh. the peripheral function control registers are allocated them. all addre sses within the sfr, which have nothing allocated are reserved for future use and cannot be accessed by users. figure 3.2 memory map of r8c/21 group undefined instruction overflow brk instruction address match single step watchdog timer?oscillation stop detection?voltage detection address break (reserved) reset fffffh 0ffffh 0yyyyh 0xxxxh 00400h 002ffh 00000h internal rom (program rom) internal ram sfr (refer to 4. special function registers (sfrs) ) 0ffffh 0ffdch 02bffh 02400h internal rom (data flash) (1) reserved area 01300h 02000h internal rom (3) (program rom) zzzzzh notes: 1. data flash block a (1 kbyte) and b (1 kbyte) are shown. 2. the blank regions are reserved. do not access locations in these regions. 3. do not use addresses 20000h to 23fffh because these areas are used for the emulator debugger. refer to 23. notes on emulator debugger of hardware manual. part number internal rom size address 0yyyyh address zzzzzh r5f21216jfp, r5f21216kfp r5f21217jfp, r5f21217kfp r5f21218jfp, r5f21218kfp R5F2121AJFP, r5f2121akfp r5f2121cjfp, r5f2121ckfp 32 kbytes 48 kbytes 64 kbytes 96 kbytes 128 kbytes 08000h 04000h 04000h 04000h 04000h - - 13fffh 1bfffh 23fffh internal ram address 0xxxxh 00bffh 00dffh 00fffh 00fffh 00fffh 2 kbytes 2.5 kbytes 3 kbytes 5 kbytes 6 kbytes size address 0ssssh - - - 037ffh 03bffh internal ram 03000h 0ssssh
r8c/20 group, r8c/21 group 4. special function registers (sfrs) rev.2.00 aug 27, 2008 page 15 of 41 rej03b0120-0200 4. special function registers (sfrs) an sfr (special function register) is a co ntrol register for a peripheral function. table 4.1 to table 4.6 list the sfr information. table 4.1 sfr information (1) (1) x: undefined notes: 1. the blank regions are reserved. do not access locations in these regions. 2. software reset, watchdog timer reset, and voltage monitor 2 reset do not affect this register. 3. the lvd0on bit in the ofs register is set to 1. 4. power-on reset, voltage monitor 1 reset or the lvd0on bit in the ofs register is set to 0. 5. software reset, watchdog timer reset, and voltage monitor 2 reset do not affect b2 and b3. 6. software reset, watchdog timer reset, and voltage monitor 2 reset do not affect b7. 7. software reset, the watchdog timer rest, and the voltage monitor 2 reset do not affect other than the b0 and b6. 8. the csproini bit in the ofs register is 0. address register symbol after reset 0000h 0001h 0002h 0003h 0004h processor mode register 0 pm0 00h 0005h processor mode register 1 pm1 00h 0006h system clock control register 0 cm0 01101000b 0007h system clock control register 1 cm1 00100000b 0008h 0009h 000ah protect register prcr 00h 000bh 000ch oscillation stop detection register ocd 00000100b 000dh watchdog timer reset register wdtr xxh 000eh watchdog timer start register wdts xxh 000fh watchdog timer control register wdc 00x11111b 0010h address match interrupt register 0 rmad0 00h 0011h 00h 0012h 00h 0013h address match interrupt enable register aier 00h 0014h address match interrupt register 1 rmad1 00h 0015h 00h 0016h 00h 0017h 0018h 0019h 001ah 001bh 001ch count source protect mode register cspr 00h 10000000b (8) 001dh 001eh 001fh 0020h 0021h 0022h 0023h high-speed on-chip oscillator control register 0 fra0 00h 0024h high-speed on-chip oscillator control register 1 fra1 when shipping 0025h high-speed on-chip oscillator control register 2 fra2 00h 0026h 0030h 0031h voltage detection register 1 (2) vca1 00001000b 0032h voltage detection register 2 (6) vca2 00h (3) 01000000b (4) 0033h 0034h 0035h 0036h voltage monitor 1 circuit control register (7) vw1c 0000x000b (3) 0100x001b (4) 0037h voltage monitor 2 circuit control register (5) vw2c 00h 0038h 0039h 003fh
r8c/20 group, r8c/21 group 4. special function registers (sfrs) rev.2.00 aug 27, 2008 page 16 of 41 rej03b0120-0200 table 4.2 sfr information (2) (1) x: undefined notes: 1. the blank regions are reserved. do not access locations in these regions. 2. selected by the iicsel bit in the pmr register. address register symbol after reset 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h timer rd0 interrupt control register trd0ic xxxxx000b 0049h timer rd1 interrupt control register trd1ic xxxxx000b 004ah timer re interrupt control register treic xxxxx000b 004bh 004ch 004dh key input interrupt control register kupic xxxxx000b 004eh a/d conversion interrupt control register adic xxxxx000b 004fh ssu interrupt control register/iic bus interrupt control register (2) ssuic/iicic xxxxx000b 0050h 0051h uart0 transmit interrupt control register s0tic xxxxx000b 0052h uart0 receive interrupt control register s0ric xxxxx000b 0053h uart1 transmit interrupt control register s1tic xxxxx000b 0054h uart1 receive interrupt control register s1ric xxxxx000b 0055h int2 interrupt control register int2ic xx00x000b 0056h timer ra interrupt control register traic xxxxx000b 0057h 0058h timer rb interrupt control register trbic xxxxx000b 0059h int1 interrupt control register int1ic xx00x000b 005ah int3 interrupt control register int3ic xx00x000b 005bh 005ch 005dh int0 interrupt control register int0ic xx00x000b 005eh 005fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006ah 006bh 006ch 006dh 006eh 006fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007ah 007bh 007ch 007dh 007eh 007fh
r8c/20 group, r8c/21 group 4. special function registers (sfrs) rev.2.00 aug 27, 2008 page 17 of 41 rej03b0120-0200 table 4.3 sfr information (3) (1) x: undefined notes: 1. the blank regions are reserved. do not access locations in these regions. 2. selected by the iicsel bit in the pmr register. address register symbol after reset 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008ah 008bh 008ch 008dh 008eh 008fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009ah 009bh 009ch 009dh 009eh 009fh 00a0h uart0 transmit/receive mode register u0mr 00h 00a1h uart0 bit rate register u0brg xxh 00a2h uart0 transmit buffer register u0tb xxh 00a3h xxh 00a4h uart0 transmit/receive control register 0 u0c0 00001000b 00a5h uart0 transmit/receive control register 1 u0c1 00000010b 00a6h uart0 receive buffer register u0rb xxh 00a7h xxh 00a8h uart1 transmit/receive mode register u1mr 00h 00a9h uart1 bit rate register u1brg xxh 00aah uart1 transmit buffer register u1tb xxh 00abh xxh 00ach uart1 transmit/receive control register 0 u1c0 00001000b 00adh uart1 transmit/receive control register 1 u1c1 00000010b 00aeh uart1 receive buffer register u1rb xxh 00afh xxh 00b0h 00b1h 00b2h 00b3h 00b4h 00b5h 00b6h 00b7h 00b8h ss control register h/iic bus control register 1 (2) sscrh/iccr1 00h 00b9h ss control register l/iic bus control register 2 (2) sscrl/iccr2 0 1111101b 00bah ss mode register/iic bus mode register 1 (2) ssmr/icmr 00011000b 00bbh ss enable register/iic bus interrupt enable register (2) sser/icier 00h 00bch ss status register/iic bus status register (2) sssr/icsr 00h/0000x000b 00bdh ss mode register 2/slave address register (2) ssmr2/sar 00h 00beh ss transmit data register/iic bus transmit data register (2) sstdr/icdrt ffh 00bfh ss receive data register/iic bus receive data register (2) ssrdr/icdrr ffh
r8c/20 group, r8c/21 group 4. special function registers (sfrs) rev.2.00 aug 27, 2008 page 18 of 41 rej03b0120-0200 table 4.4 sfr information (4) (1) x: undefined note: 1. the blank regions are reserved. do not access locations in these regions. address register symbol after reset 00c0h a/d register ad xxh 00c1h xxh 00c2h 00c3h 00c4h 00c5h 00c6h 00c7h 00c8h 00c9h 00cah 00cbh 00cch 00cdh 00ceh 00cfh 00d0h 00d1h 00d2h 00d3h 00d4h a/d control register 2 adcon2 00h 00d5h 00d6h a/d control register 0 adcon0 00h 00d7h a/d control register 1 adcon1 00h 00d8h 00d9h 00dah 00dbh 00dch 00ddh 00deh 00dfh 00e0h port p0 register p0 xxh 00e1h port p1 register p1 xxh 00e2h port p0 direction register pd0 00h 00e3h port p1 direction register pd1 00h 00e4h port p2 register p2 xxh 00e5h port p3 register p3 xxh 00e6h port p2 direction register pd2 00h 00e7h port p3 direction register pd3 00h 00e8h port p4 register p4 xxh 00e9h 00eah port p4 direction register pd4 00h 00ebh 00ech port p6 register p6 xxh 00edh 00eeh port p6 direction register pd6 00h 00efh 00f0h 00f1h 00f2h 00f3h 00f4h 00f5h uart1 function select register u1sr xxh 00f6h 00f7h 00f8h port mode register pmr 00h 00f9h external input enable register inten 00h 00fah int input filter select register intf 00h 00fbh key input enable register kien 00h 00fch pull-up control register 0 pur0 00h 00fdh pull-up control register 1 pur1 xx00xx00b 00feh 00ffh
r8c/20 group, r8c/21 group 4. special function registers (sfrs) rev.2.00 aug 27, 2008 page 19 of 41 rej03b0120-0200 table 4.5 sfr information (5) (1) x: undefined note: 1. the blank regions are reserved. do not access locations in these regions. address register symbol after reset 0100h timer ra control register tracr 00h 0101h timer ra i/o control register traioc 00h 0102h timer ra mode register tramr 00h 0103h timer ra prescaler register trapre ffh 0104h timer ra register tra ffh 0105h 0106h lin control register lincr 00h 0107h lin status register linst 00h 0108h timer rb control register trbcr 00h 0109h timer rb one-shot control register trbocr 00h 010ah timer rb i/o control register trbioc 00h 010bh timer rb mode register trbmr 00h 010ch timer rb prescaler register trbpre ffh 010dh timer rb secondary register trbsc ffh 010eh timer rb primary trbpr ffh 010fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h timer re counter data register tresec 00h 0119h timer re compare data register tremin 00h 011ah 011bh 011ch timer re control register 1 trecr1 00h 011dh timer re control register 2 trecr2 00h 011eh timer re count source select register trecsr 00001000b 011fh 0120h 0121h 0122h 0123h 0124h 0125h 0126h 0127h 0128h 0129h 012ah 012bh 012ch 012dh 012eh 012fh 0130h 0131h 0132h 0133h 0134h 0135h 0136h 0137h timer rd start register trdstr 11111100b 0138h timer rd mode register trdmr 00001110b 0139h timer rd pwm mode register trdpmr 10001000b 013ah timer rd function control register trdfcr 10000000b 013bh timer rd output master enable register 1 trdoer1 ffh 013ch timer rd output master enable register 2 trdoer2 0 1111111b 013dh timer rd output control register trdocr 00h 013eh timer rd digital filter function select register 0 trddf0 00h 013fh timer rd digital filter function select register 1 trddf1 00h
r8c/20 group, r8c/21 group 4. special function registers (sfrs) rev.2.00 aug 27, 2008 page 20 of 41 rej03b0120-0200 table 4.6 sfr information (6) (1) x: undefined notes: 1. the blank regions are reserved. do not access locations in these regions. 2. the ofs register cannot be changed by a program. use a flash programmer to write to it. address register symbol after reset 0140h timer rd control register 0 trdcr0 00h 0141h timer rd i/o control register a0 trdiora0 10001000b 0142h timer rd i/o control register c0 trdiorc0 10001000b 0143h timer rd status register 0 trdsr0 11100000b 0144h timer rd interrupt enable register 0 trdier0 11100000b 0145h timer rd pwm mode output level control register 0 trdpocr0 1111 1000b 0146h timer rd counter 0 trd0 00h 0147h 00h 0148h timer rd general register a0 trdgra0 ffh 0149h ffh 014ah timer rd general register b0 trdgrb0 ffh 014bh ffh 014ch timer rd general register c0 trdgrc0 ffh 014dh ffh 014eh timer rd general register d0 trdgrd0 ffh 014fh ffh 0150h timer rd control register 1 trdcr1 00h 0151h timer rd i/o control register a1 trdiora1 10001000b 0152h timer rd i/o control register c1 trdiorc1 10001000b 0153h timer rd status register 1 trdsr1 11000000b 0154h timer rd interrupt enable register 1 trdier1 11100000b 0155h timer rd pwm mode output level control register 1 trdpocr1 1111 1000b 0156h timer rd counter 1 trd1 00h 0157h 00h 0158h timer rd general register a1 trdgra1 ffh 0159h ffh 015ah timer rd general register b1 trdgrb1 ffh 015bh ffh 015ch timer rd general register c1 trdgrc1 ffh 015dh ffh 015eh timer rd general register d1 trdgrd1 ffh 015fh ffh 01b0h 01b1h 01b2h 01b3h flash memory control register 4 fmr4 01000000b 01b4h 01b5h flash memory control register 1 fmr1 1000000xb 01b6h 01b7h flash memory control register 0 fmr0 00000001b 01b8h 01b9h 01bah 01bbh 01bch 01bdh 01beh 01bfh ffffh option function select register ofs (note 2)
r8c/20 group, r8c/21 group 5. electrical characteristics rev.2.00 aug 27, 2008 page 21 of 41 rej03b0120-0200 5. electrical characteristics notes: 1. v cc = 2.7 to 5.5 v at topr = -40 to 85 c (j version) / -40 to 125 c (k version), unless otherwise specified. 2. the average output current indicates the av erage value of current measured during 100 ms. table 5.1 absolute maximum ratings symbol parameter condition rated value unit v cc /av cc supply voltage -0.3 to 6.5 v v i input voltage -0.3 to v cc +0.3 v v o output voltage -0.3 to v cc +0.3 v p d power dissipation -40 c to p r 85 c 300 mw 85 c < topr 125 c 125 mw t opr operating ambient temperature -40 to 85 (j version) / -40 to 125 (k version) c t stg storage temperature -65 to 150 c table 5.2 recommended operating conditions symbol parameter conditions standard unit min. typ. max. v cc /av cc supply voltage 2.7 ? 5.5 v v ss /av cc supply voltage ? 0 ? v v ih input ?h? voltage 0.8v cc ? v cc v v il input ?l? voltage 0 ? 0.2v cc v i oh(sum) peak sum output ?h? current sum of all pins i oh (peak) ?? -60 ma i oh(peak) peak output ?h? current ?? -10 ma i oh(avg) average output ?h? current ?? -5 ma i ol(sum) peak sum output ?l? currents sum of all pins i ol (peak) ?? 60 ma i ol(peak) peak output ?l? currents ?? 10 ma i ol(avg) average output ?l? current ?? 5ma f (xin) xin clock input oscillation frequency 3.0 v v cc 5.5 v -40 c topr 85 c 0 ? 20 mhz 3.0 v v cc 5.5 v -40 c topr 125 c 0 ? 16 mhz 2.7 v v cc < 3.0 v 0 ? 10 mhz ? system clock ocd2 = 0 when xin clock is selected. 3.0 v v cc 5.5 v -40 c topr 85 c 0 ? 20 mhz 3.0 v v cc 5.5 v -40 c topr 125 c 0 ? 16 mhz 2.7 v v cc < 3.0 v 0 ? 10 mhz ocd2 = 1 when on-chip oscillator clock is selected. fra01 = 0 when low-speed on- chip oscillator clock is selected. ? 125 ? khz fra01 = 1 when high-speed on- chip oscillator clock is selected. 3.0 v v cc 5.5 v -40 c topr 85 c ?? 20 mhz fra01 = 1 when high-speed on- chip oscillator clock is selected. ?? 10 mhz
r8c/20 group, r8c/21 group 5. electrical characteristics rev.2.00 aug 27, 2008 page 22 of 41 rej03b0120-0200 notes: 1. v cc = av cc = 2.7 to 5.5 v at topr = -40 to 85 c (j version) / -40 to 125 c (k version), unless otherwise specified. 2. when analog input voltage exceeds reference voltage, a/d conv ersion result is 3ffh in 10-bit mode, ffh in 8-bit mode. figure 5.1 ports p0 to p4, p6 timing measurement circuit table 5.3 a/d converter characteristics symbol parameter conditions standard unit min. typ. max. ? resolution v ref = av cc ?? 10 bits ? absolute accuracy 10-bit mode ad = 10 mhz, v ref = av cc = 5.0 v ?? 3 lsb 8-bit mode ad = 10 mhz, v ref = av cc = 5.0 v ?? 2 lsb 10-bit mode ad = 10 mhz, v ref = av cc = 3.3 v ?? 5 lsb 8-bit mode ad = 10 mhz, v ref = av cc = 3.3 v ?? 2 lsb r ladder resistor ladder v ref = av cc 10 ? 40 k ? t conv conversion time 10-bit mode ad = 10 mhz, v ref = av cc = 5.0 v 3.3 ?? s 8-bit mode ad = 10 mhz, v ref = av cc = 5.0 v 2.8 ?? s v ref reference voltage 2.7 ? av cc v v ia analog input voltage (2) 0 ? av cc v ? a/d operating clock frequency without sample & hold 0.25 ? 10 mhz with sample & hold 1 ? 10 mhz p0 p3 p2 p1 p6 p4 30pf
r8c/20 group, r8c/21 group 5. electrical characteristics rev.2.00 aug 27, 2008 page 23 of 41 rej03b0120-0200 notes: 1. v cc = 2.7 to 5.5 v at topr = -40 to 85 c (j version) / -40 to 125 c (k version), unless otherwise specified. 2. definition of programming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 100 or 1,000), each block can be erased n times. for example, if 1,024 1-byte writes are performed to different addresses in block a, a 1 kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. endurance to guarantee all electrical characteristics after program and erase (1 to min. value can be guaranteed). 4. in a system that executes multiple programming operations , the actual erasure endurance can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before per forming an erase operation. for example, when programming groups of 16 bytes, the effective number of rewrites can be mi nimized by programming up to 128 groups before erasing them all in one operation. it is al so advisable to retain data on the erasure endurance of each block and limit the number of eras e operations to a certain number. 5. if error occurs during block erase, attempt to execute the clear status register command, then the block erase command at least three times until the erase error does not occur. 6. customers desiring program/erase failure rate information should contact their renesas te chnical support representative. 7. the data hold time includes time that the power supply is off or the clock is not supplied. table 5.4 flash memory (program rom) electrical characteristics symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (2) r8c/20 group 100 (3) ?? times r8c/21 group 1,000 (3) ?? times ? byte program time ? 50 400 s ? block erase time ? 0.4 9 s t d(sr-sus) time delay from suspend request until erase suspend ?? 97 + cpu clock 6 cycle s ? interval from erase start/restart until following suspend request 650 ?? s ? interval from program start/restart until following suspend request 0 ?? ns ? time from suspend until program/erase restart ?? 3 + cpu clock 4 cycle s ? program, erase voltage 2.7 ? 5.5 v ? read voltage 2.7 ? 5.5 v ? program, erase temperature 0 ? 60 c ? data hold time (7) ambient temperature = 55 c20 ?? year
r8c/20 group, r8c/21 group 5. electrical characteristics rev.2.00 aug 27, 2008 page 24 of 41 rej03b0120-0200 notes: 1. v cc = 2.7 to 5.5 v at topr = -40 to 85 c (j version) / -40 to 125 c (k version), unless otherwise specified. 2. definition of programming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 10,000), each block can be erased n times. for example, if 1,024 1-byte writes are performed to different addresses in block a, a 1 kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. minimum endurance to guarantee all electrical characteristics after program and erase (1 to min. value can be guaranteed). 4. standard of block a and block b when program and erase endurance exceeds 1,000 times. byte program time to 1,000 times are the same as that in program rom. 5. in a system that executes multiple programming operations , the actual erasure endurance can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before per forming an erase operation. for example, when programming groups of 16 bytes, the effective number of rewrites can be mi nimized by programming up to 128 groups before erasing them all in one operation. in a ddition, averaging the erasur e endurance between blocks a and b can further reduce the actual erasure endur ance. it is also advisable to retain dat a on the erasure endurance of each block and limit the number of erase operations to a certain number. 6. if error occurs during block erase, attempt to execute the clear status register command, then the block erase command at least three times until the erase error does not occur. 7. customers desiring program/erase failure rate information should contact their renesas te chnical support representative. 8. 125 c for k version. 9. the data hold time includes time that the power supply is off or the clock is not supplied. table 5.5 flash memory (data flash block a, block b) electrical characteristics (4) symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (2) 10,000 (3) ?? times ? byte program time (program/erase endurance 1,000 times) ? 50 400 s ? byte program time (program/erase endurance > 1,000 times) ? 65 ? s ? block erase time (program/erase endurance 1,000 times) ? 0.2 9 s ? block erase time (program/erase endurance > 1,000 times) ? 0.3 ? s t d(sr-sus) time delay from suspend request until erase suspend ?? 97 + cpu clock 6 cycle s ? interval from erase start/restart until following suspend request 650 ?? s ? interval from program start/restart until following suspend request 0 ?? ns ? time from suspend until program/erase restart ?? 3 + cpu clock 4 cycle s ? program, erase voltage 2.7 ? 5.5 v ? read voltage 2.7 ? 5.5 v ? program, erase temperature -40 ? 85 (8) c ? data hold time (9) ambient temperature = 55 c20 ?? year
r8c/20 group, r8c/21 group 5. electrical characteristics rev.2.00 aug 27, 2008 page 25 of 41 rej03b0120-0200 figure 5.2 time delay until suspend notes: 1. the measurement condition is v cc = 2.7 v to 5.5 v and topr = -40 c to 85 c (j version) / -40 c to 125 c (k version). 2. necessary time until the voltage detection circuit operates when setting to 1 again after setting the vca26 bit in the vca2 register to 0. 3. hold v det2 > v det1 . 4. this parameter shows the voltage detection level when the power supply drops. the voltage detection level when the power supply rises is higher than the voltage detection le vel when the power supply drops by approximately 0.1 v. 5. time until the voltage monitor 1 rese t is generated after the voltage passes v det1 when v cc falls. when using the digital filter, its sampling time is added to t d(vdet1-a) . when using the voltage monitor 1 reset, maintain this time until v cc = 2.0 v after the voltage passes v det1 when the power supply falls. notes: 1. the measurement condition is v cc = 2.7 v to 5.5 v and topr = -40 c to 85 c (j version) / -40 c to 125 c (k version). 2. time until the voltage monitor 2 reset/interrupt request is generated since the voltage passes v det2 . 3. necessary time until the voltage detection circuit operates when setting to 1 again after setting the vca27 bit in the vca2 register to 0. 4. hold v det2 > v det1 . 5. when using the digital filter, its sampling time is added to t d(vdet2-a) . when using the voltage monitor 2 reset, maintain this time until v cc = 2.0 v after the voltage passes v det2 when the power supply falls. table 5.6 voltage detection 1 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det1 voltage detection level (3, 4) 2.70 2.85 3.00 v t d(vdet1-a) voltage monitor 1 reset generation time (5) ? 40 200 s ? voltage detection circuit self power consumption vca26 = 1, v cc = 5.0 v ? 0.6 ? a t d(e-a) waiting time until voltage detection circuit operation starts (2) ?? 100 s vccmin mcu operating voltage minimum value 2.70 ?? v table 5.7 voltage detection 2 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det2 voltage detection level (4) 3.3 3.6 3.9 v t d(vdet2-a) voltage monitor 2 reset/interrupt request generation time (2, 5) ? 40 200 s ? voltage detection circuit self power consumption vca27 = 1, v cc = 5.0v ? 0.6 ? a t d(e-a) waiting time until voltage detection circuit operation starts (3) ?? 100 s fmr46 suspend request (maskable interrupt request) fixed time t d(sr-sus) clock-dependent time access restart
r8c/20 group, r8c/21 group 5. electrical characteristics rev.2.00 aug 27, 2008 page 26 of 41 rej03b0120-0200 notes: 1. topr = -40 c to 85 c (j version) / -40 c to 125 c (k version), unless otherwise specified. 2. this condition (the minimum value of external power v cc rise gradient) does not apply if v por2 1.0 v. 3. to use the power-on reset function, enable voltage monitor 1 reset by setting the lvd1on bit in the ofs register to 0, the vw1c0 and vw1c6 bits in the vw1c register to 1 respectively, and the vca26 bit in the vca2 register to 1. 4. t w(por1) indicates the duration the external power v cc must be held below the effective voltage (v por1 ) to enable a power on reset. when turning on the power for the first time, maintain tw(por1) for 30s or more if -20 c topr 125 c, maintain t w(por1) for 3,000s or more if -40 c topr < -20 c. figure 5.3 power-on reset circuit electrical characteristics table 5.8 power-on reset circuit, voltage monitor 1 reset circuit electrical characteristics (3) symbol parameter condition standard unit min. typ. max. v por1 power-on reset valid voltage (4) ?? 0.1 v v por2 power-on reset or voltage monitor 1 valid voltage 0 ? vdet1 v trth external power v cc rise gradient v cc 3.6 v 20 (2) ?? mv/msec v cc > 3.6 v 20 (2) ? 2,000 mv/msec 32 1 foco-s v det1 (3) v por1 t w(por1) v det1 (3) v por2 2.0 v trth trth external power vcc internal reset signal (?l? valid) sampling time (1, 2) t d(vdet1-a) 32 1 foco-s notes: 1. when using the voltage monitor 1 digital filter, ensure vcc is 2.0 v or higher during the sampling time. 2. the sampling clock can be selected. refer to 6. voltage detection circuit of hardware manual for details. 3. v det1 indicates the voltage detection level of the voltage detection 1 circuit. refer to 6. voltage detection circuit of hardware manual for details.
r8c/20 group, r8c/21 group 5. electrical characteristics rev.2.00 aug 27, 2008 page 27 of 41 rej03b0120-0200 notes: 1. v cc = 2.7 v to 5.5 v, topr = -40 c to 85 c (j version) / -40 c to 125 c (k version), unless otherwise specified. 2. the standard value shows when the reset is deasserted for the fra1 register. note: 1. v cc = 2.7 v to 5.5 v, topr = -40 c to 85 c (j version) / -40 c to 125 c (k version), unless otherwise specified. notes: 1. the measurement condition is v cc = 2.7 to 5.5 v and topr = -40 c to 85 c (j version) / -40 c to 125 c (k version), unless otherwise specified. 2. waiting time until the internal power s upply generation circuit stabilizes during power-on. 3. time until cpu clock supply starts since the interrupt is acknowledged to exit stop mode. table 5.9 high-speed on-chip oscillator circuit electrical characteristics symbol parameter condition standard unit min. typ. max. foco40m high-speed on-chip oscill ator frequency temperature ? supply voltage dependence v cc = 4.75 v to 5.25 v, 0 c topr 60 c (2) 39.2 40 40.8 mhz v cc = 3.0 v to 5.25 v, -20 c topr 85 c (2) 38.8 40 41.2 mhz v cc = 3.0 v to 5.5 v, -40 c topr 85 c (2) 38.4 40 41.6 mhz v cc = 3.0 v to 5.5 v, -40 c topr 125 c (2) 38.0 40 42.0 mhz v cc = 2.7 v to 5.5 v, -40 c topr 125 c (2) 37.6 40 42.4 mhz ? the value of the fra1 register when the reset is deasserted 08h 40 f7h ? ? high-speed on-chip oscillator adjustment range adjust the fra1 register to -1 bit (the value when the reset is deasserted) ? + 0.3 ? mhz ? oscillation st ability time ? 10 100 s ? self power consumption when high-speed on-chip oscillator oscillating v cc = 5.0 v, topr = 25 c ? 600 ? a table 5.10 low-speed on-chip oscillator circuit electrical characteristics symbol parameter condition standard unit min. typ. max. foco-s low-speed on-chip oscillator frequency 40 125 250 khz ? oscillation st ability time ? 10 100 s ? self power consumption when low-speed on-chip oscillator oscillating v cc = 5.0 v, topr = 25 c ? 15 ? a table 5.11 power supply circui t timing characteristics symbol parameter condition standard unit min. typ. max. t d(p-r) time for internal power supply stabilization during power-on (2) 1 ? 2000 s t d(r-s) stop exit time (3) ?? 150 s
r8c/20 group, r8c/21 group 5. electrical characteristics rev.2.00 aug 27, 2008 page 28 of 41 rej03b0120-0200 notes: 1. v cc = 2.7 to 5.5 v, v ss = 0 v at topr = -40 to 85 c (j version) / -40 to 125 c (k version), unless otherwise specified. 2. 1t cyc = 1/f1(s) table 5.12 timing requirements of clock synchronous serial i/o with chip select (1) symbol parameter conditions standard unit min. typ. max. t sucyc ssck clock cycle time 4 ?? t cyc (2) t hi ssck clock ?h? width 0.4 ? 0.6 t sucyc t lo ssck clock ?l? width 0.4 ? 0.6 t sucyc t rise ssck clock rising time master ?? 1 t cyc (2) slave ?? 1 s t fall ssck clock falling time master ?? 1 t cyc (2) slave ?? 1 s t su sso, ssi data input setup time 100 ?? ns t h sso, ssi data input hold time 1 ?? t cyc (2) t lead scs setup time slave 1t cyc + 50 ?? ns t lag scs hold time slave 1t cyc + 50 ?? ns t od sso, ssi data output delay time ?? 1 t cyc (2) t sa ssi slave access time ?? 1t cyc + 100 ns t or ssi slave out open time ?? 1t cyc + 100 ns
r8c/20 group, r8c/21 group 5. electrical characteristics rev.2.00 aug 27, 2008 page 29 of 41 rej03b0120-0200 figure 5.4 i/o timing of clock synchronous serial i/o with chip select (master) v ih or v oh v ih or v oh t hi t lo t hi t fall t rise t lo t sucyc t od t h t su scs (output) ssck (output) (cpos = 1) ssck (output) (cpos = 0) sso (output) ssi (input) 4-wire bus communication mode, master, cphs = 1 v ih or v oh v ih or v oh t hi t lo t hi t fall t rise t lo t sucyc t od t h t su scs (output) ssck (output) (cpos = 1) ssck (output) (cpos = 0) sso (output) ssi (input) 4-wire bus communication mode, master, cphs = 0 cphs, cpos: bits in ssmr register
r8c/20 group, r8c/21 group 5. electrical characteristics rev.2.00 aug 27, 2008 page 30 of 41 rej03b0120-0200 figure 5.5 i/o timing of clock synchronous serial i/o with chip select (slave) v ih or v oh v ih or v oh scs (input) ssck (input) (cpos = 1) ssck (input) (cpos = 0) sso (input) ssi (output) 4-wire bus communication mode, slave, cphs = 1 v ih or v oh v ih or v oh t hi t lo t hi t fall t rise t lo t sucyc t h t su scs (input) ssck (input) (cpos = 1) ssck (input) (cpos = 0) sso (input) ssi (output) 4-wire bus communication mode, slave, cphs = 0 t od t lead t sa t lag t or t hi t lo t hi t fall t rise t lo t sucyc t h t su t od t lead t sa t lag t or cphs, cpos: bits in ssmr register
r8c/20 group, r8c/21 group 5. electrical characteristics rev.2.00 aug 27, 2008 page 31 of 41 rej03b0120-0200 figure 5.6 i/o timing of clock synchronous serial i/o with chip select (clock synchronous communication mode) v ih or v oh t hi t lo t sucyc t od t h t su ssck sso (output) ssi (input) v ih or v oh
r8c/20 group, r8c/21 group 5. electrical characteristics rev.2.00 aug 27, 2008 page 32 of 41 rej03b0120-0200 notes: 1. v cc = 2.7 to 5.5 v, v ss = 0v at topr = -40 to 85 c (j version) / -40 to 125 c (k version), unless otherwise specified. 2. 1t cyc = 1/f1(s) figure 5.7 i/o timing of i 2 c bus interface table 5.13 timing requirements of i 2 c bus interface (1) symbol parameter conditions standard unit min. typ. max. t scl scl input cycle time 12t cyc + 600 (2) ?? ns t sclh scl input ?h? width 3t cyc + 300 (2) ?? ns t scll scl input ?l? width 5t cyc + 300 (2) ?? ns t sf scl, sda input falling time ?? 300 ns t sp scl, sda input spike pulse rejection time ?? 1t cyc (2) ns t buf sda input bus-free time 5t cyc (2) ?? ns t stah start condition input hole time 3t cyc (2) ?? ns t stas retransmit start condition input setup time 3t cyc (2) ?? ns t stop stop condition input setup time 3t cyc (2) ?? ns t soas data input setup time 1t cyc + 20 (2) ?? ns t sdah data input hold time 0 ?? ns sda scl t buf v ih v il p (2) s (1) t stah t sclh t scll t sf t sr t scl t sdah sr (3) p (2) t sdas t stas t sp t stop notes: 1. start condition 2. stop condition 3. retransmit ?start? condition
r8c/20 group, r8c/21 group 5. electrical characteristics rev.2.00 aug 27, 2008 page 33 of 41 rej03b0120-0200 note: 1. v cc = 4.2 to 5.5 v at topr = -40 to 85 c (j version) / -40 to 125 c (k version), f(xin) = 20 mhz, unless otherwise specified. table 5.14 electrical characteristics (1) [v cc = 5 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage except xout i oh = -5 ma v cc ? 2.0 ? v cc v i oh = -200 av cc ? 0.3 ? v cc v xout drive capacity high i oh = -1 ma v cc ? 2.0 ? v cc v drive capacity low i oh = -500 av cc ? 2.0 ? v cc v v ol output ?l? voltage except xout i ol = 5 ma ?? 2.0 v i ol = 200 a ?? 0.45 v xout drive capacity high i ol = 1 ma ?? 2.0 v drive capacity low i ol = 500 a ?? 2.0 v v t+- v t- hysteresis int0 , int1 , int2 , int3 , ki0 , ki1 , ki2 , ki3 , traio, rxd0, rxd1, clk0, ssi, scl, sda, sso 0.1 0.5 ? v reset 0.1 1.0 ? v i ih input ?h? current vi = 5 v, v cc = 5 v ?? 5.0 a i il input ?l? current vi = 0 v, v cc = 5 v ?? -5.0 a r pullup pull-up resistance vi = 0 v, v cc = 5 v 30 50 167 k ? r fxin feedback resistance xin ? 1.0 ? m ? v ram ram hold voltage during stop mode 2.0 ?? v
r8c/20 group, r8c/21 group 5. electrical characteristics rev.2.00 aug 27, 2008 page 34 of 41 rej03b0120-0200 table 5.15 electrical characteristics (2) [v cc = 5 v] (topr = -40 to 85 c (j version) / -40 to 125 c (k version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 3.3 to 5.5 v) in single-chip mode, the output pins are open and other pins are v ss high-clock mode xin = 20 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 11.0 22.0 ma xin = 16 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 8.8 17.6 ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 5.8 ? ma xin = 20 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 5.0 ? ma xin = 16mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 3.8 ? ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2.8 ? ma high-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator on foco = 10 mhz low-speed on-chip oscillator on = 125 khz no division ? 5.8 11.6 ma xin clock off high-speed on-chip oscillator on foco= 10 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2.5 ? ma low-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 fmr47 = 1 ? 143 286 a wait mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca20 = 0 vca26 = vca27 = 0 ? 53 106 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca20 = 0 vca26 = vca27 = 0 ? 38 76 a stop mode topr = 25 c xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca26 = vca27 = 0 ? 0.8 3.0 a stop mode topr = 85 c xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca26 = vca27 = 0 ? 1.2 ? a stop mode topr = 125 c xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca26 = vca27 = 0 ? 4.0 ? a
r8c/20 group, r8c/21 group 5. electrical characteristics rev.2.00 aug 27, 2008 page 35 of 41 rej03b0120-0200 timing requirements (unle ss otherwise specified: v cc = 5 v, v ss = 0 v at topr = 25 c) [v cc = 5 v] figure 5.8 xin input timing diagram when v cc = 5 v figure 5.9 traio input timing diagram when v cc = 5 v table 5.16 xin input symbol parameter standard unit min. max. t c(xin) xin input cycle time 50 ? ns t wh(xin) xin input ?h? width 25 ? ns t wl(xin) xin input ?l? width 25 ? ns table 5.17 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 100 ? ns t wh(traio) traio input ?h? width 40 ? ns t wl(traio) traio input ?l? width 40 ? ns vcc = 5v xin input t wh(xin) t c(xin) t wl(xin) vcc = 5v traio input t wh(traio) t c(traio) t wl(traio)
r8c/20 group, r8c/21 group 5. electrical characteristics rev.2.00 aug 27, 2008 page 36 of 41 rej03b0120-0200 i = 0 or 1 figure 5.10 serial interface timing diagram when v cc = 5 v notes: 1. when selecting the digital filter by the inti input filter select bit, use the inti input high width to the greater value, either (1/digital filter cloc k frequency x 3) or the minimum value of standard. 2. when selecting the digital filter by the inti input filter select bit, use the inti input low width to the greater value, either (1/digital filter cloc k frequency x 3) or the minimum value of standard. figure 5.11 external interrupt inti input timing diagram when v cc = 5 v (i = 0 to 3) table 5.18 serial interface symbol parameter standard unit min. max. t c(ck) clk0 input cycle time 200 ? ns t w(ckh) clk0 input ?h? width 100 ? ns t w(ckl) clk0 input ?l? width 100 ? ns t d(c-q) txdi output delay time ? 50 ns t h(c-q) txdi hold time 0 ? ns t su(d-c) rxdi input setup time 50 ? ns t h(c-d) rxdi input hold time 90 ? ns table 5.19 external interrupt inti (i = 0 to 3) input symbol parameter standard unit min. max. t w(inh) inti input ?h? width 250 (1) ? ns t w(inl) inti input ?l? width 250 (2) ? ns i = 0 or 1 vcc = 5v clk 0 txd i rxd i t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) i = 0 to 3 vcc = 5v int i input t w(inl) t w(inh)
r8c/20 group, r8c/21 group 5. electrical characteristics rev.2.00 aug 27, 2008 page 37 of 41 rej03b0120-0200 note: 1. v cc = 2.7 to 3.3 v at topr = -40 to 85 c (j version) / -40 to 125 c (k version), f(xin) = 10 mhz, unless otherwise specified. table 5.20 electrical characteristics (3) [v cc = 3 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage except xout i oh = -1 ma v cc ? 0.5 ? v cc v xout drive capacity high i oh = -0.1 ma v cc ? 0.5 ? v cc v drive capacity low i oh = -50 av cc ? 0.5 ? v cc v v ol output ?l? voltage except xout i ol = 1 ma ?? 0.5 v xout drive capacity high i ol = 0.1 ma ?? 0.5 v drive capacity low i ol = 50 a ?? 0.5 v v t+- v t- hysteresis int0 , int1 , int2 , int3 , ki0 , ki1 , ki2 , ki3 , traio, rxd0, rxd1, clk0, ssi, scl, sda, sso 0.1 0.3 ? v reset 0.1 0.4 ? v i ih input ?h? current vi = 3 v, v cc = 3 v ?? 4.0 a i il input ?l? current vi = 0 v, v cc = 3 v ?? -4.0 a r pullup pull-up resistance vi = 0 v, v cc = 3 v 66 160 500 k ? r fxin feedback resistance xin ? 3.0 ? m ? v ram ram hold voltage during stop mode 2.0 ?? v
r8c/20 group, r8c/21 group 5. electrical characteristics rev.2.00 aug 27, 2008 page 38 of 41 rej03b0120-0200 table 5.21 electrical characteristics (4) [v cc = 3 v] (topr = -40 to 85 c (j version) / -40 to 125 c (k version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 2.7 to 3.3 v) in single-chip mode, the output pins are open and other pins are v ss high-clock mode xin = 20 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 10.5 21.0 ma xin = 16 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 8.3 16.6 ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 5.3 10.6 ma xin = 20 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 4.5 ? ma xin = 16 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 3.3 ? ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2.3 ? ma high-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator on foco = 10 mhz low-speed on-chip oscillator on = 125 khz no division ? 5.6 11.2 ma xin clock off high-speed on-chip oscillator on foco = 10 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2.4 ? ma low-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 fmr47 = 1 ? 138 276 a wait mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca20 = 0 vca26 = vca27 = 0 ? 48 96 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca20 = 0 vca26 = vca27 = 0 ? 35 70 a stop mode topr = 25 c xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca26 = vca27 = 0 ? 0.7 3.0 a stop mode topr = 85 c xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca26 = vca27 = 0 ? 1.1 ? a stop mode topr = 125 c xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca26 = vca27 = 0 ? 3.8 ? a
r8c/20 group, r8c/21 group 5. electrical characteristics rev.2.00 aug 27, 2008 page 39 of 41 rej03b0120-0200 timing requirements (unle ss otherwise specified: v cc = 3 v, v ss = 0v at topr = 25 c) [v cc = 3 v] figure 5.12 xin input timing diagram when v cc = 3 v figure 5.13 traio input timing diagram when v cc = 3 v table 5.22 xin input symbol parameter standard unit min. max. t c(xin) xin input cycle time 100 ? ns t wh(xin) xin input ?h? width 40 ? ns t wl(xin) xin input ?l? width 40 ? ns table 5.23 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 300 ? ns t wh(traio) traio input ?h? width 120 ? ns t wl(traio) traio input ?l? width 120 ? ns vcc = 3v xin input t wh(xin) t c(xin) t wl(xin) vcc = 3v traio input t wh(traio) t c(traio) t wl(traio)
r8c/20 group, r8c/21 group 5. electrical characteristics rev.2.00 aug 27, 2008 page 40 of 41 rej03b0120-0200 i = 0 or 1 figure 5.14 serial interface timing diagram when v cc = 3 v notes: 1. when selecting the digital filter by the inti input filter select bit, use the inti input high width to the greater value, either (1/digital filter cloc k frequency x 3) or the minimum value of standard. 2. when selecting the digital filter by the inti input filter select bit, use the inti input low width to the greater value, either (1/digital filter cloc k frequency x 3) or the minimum value of standard. figure 5.15 external interrupt inti input timing diagram when v cc = 3 v (i = 0 to 3) table 5.24 serial interface symbol parameter standard unit min. max. t c(ck) clk0 input cycle time 300 ? ns t w(ckh) clk0 input ?h? width 150 ? ns t w(ckl) clk0 input ?l? width 150 ? ns t d(c-q) txdi output delay time ? 80 ns t h(c-q) txdi hold time 0 ? ns t su(d-c) rxdi input setup time 70 ? ns t h(c-d) rxdi input hold time 90 ? ns table 5.25 external interrupt inti (i = 0 to 3) input symbol parameter standard unit min. max. t w(inh) inti input ?h? width 380 (1) ? ns t w(inl) inti input ?l? width 380 (2) ? ns i = 0 or 1 vcc = 3v clk 0 txd i rxd i t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) i = 0 to 3 vcc = 3v int i input t w(inl) t w(inh)
r8c/20 group, r8c/21 group package dimensions rev.2.00 aug 27, 2008 page 41 of 41 rej03b0120-0200 package dimensions diagrams showing the latest package dimensions and mounting information are available in the ?packages? section of the renesas technology website. terminal cross section b 1 c 1 bp c 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. detail f l 1 c a l a 1 a 2 * 3 f 48 37 36 25 24 13 12 1 * 1 * 2 x index mark y z e z d b p e h e h d d e previous code jeita package code renesas code plqp0048kb-a 48p6q-a mass[typ.] 0.2g p-lqfp48-7x7-0.50 1.0 0.125 0.20 0.75 0.75 0.08 0.20 0.145 0.09 0.27 0.22 0.17 max nom min dimension in millimeters symbol reference 7.1 7.0 6.9 d 7.1 7.0 6.9 e 1.4 a 2 9.2 9.0 8.8 9.2 9.0 8.8 1.7 a 0.2 0.1 0 0.65 0.5 0.35 l x 8 0 c 0.5 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1
a - 1 r8c/20 group, r8c/21 group datasheet rev. date description page summary 0.10 mar 08, 2005 ? first edition issued 0.20 sep 29, 2005 ? words standardized - clock synchronous serial interface clock synchronous serial i/o - chip-select clock synchronous interface(ssu) clock synchronous serial i/o with chip select - i 2 c bus interface(iic) i 2 c bus interface 2, 3 table1.1 r8c/20 group perfor mance, table1.2 r8c/21 group performance serial interface revised: - clock synchronous serial interface: 1 channel i 2 c bus interface (3), clock synchrono us serial i/o with chip select - power-on reset circuit added - power consumptio n value determined 5, 6 table 1.3 product information of r8c/20 group, table 1.4 product information of r8c/21 group date revised. 7 figure 1.4 pin assignment pin name revised: - p3_5/ssck(/scl) p3_5/ scl/ssck - p3_4/scs (/sda) p3_4/ sda /scs - vss vss/avss - vcc vcc/avcc - p1_5/rxd0/(traio/int1 ) p1_5/rxd0/(traio)/(int1 ) - p6_6/int2 /(txd1) p6_6/int2 /txd1 - p6_7/int3 /(rxd1) p6_7/int3 /rxd1 - note2 added 8 table 1.5 pin description - analog power supply input: line added - i 2 c bus interface (iic) i 2 c bus interface - ssu clock synchronous serial i/o with chip select 9 table 1.6 pin name information by pin number revised - pin number 1: (scl) scl - pin number 2: (sda) sda - pin number 9: vss vss/avss - pin number 11: vcc vcc/avcc - pin number 26: (txd1) txd1 - pin number 27: (rxd1) rxd1 15 table 4.1 sfr information (1) revised - 0013h: xxxxxx00b 00h 17 table 4.3 sfr information (3) revised - 00bch: 0000x000b 00h/0000x000b 18 table 4.4 sfr information (4) revised - 00d6h: 00000xxxb 00h - 00f5h: uart1 function select register added 19 table 4.5 sfr information (5) revised - 0104h: tratr tra revision history
a - 2 revision history r8c/20 group, r8c/21 group datasheet 0.20 sep 29, 2005 20 table 4.6 sfr information (6) revised - 0145h: pocr0 trdpocr0 - 0146h, 0147h: trdcnt0 trd0 - 0148h, 0149h: gra0 trdgra0 - 014ah, 014bh: grb0 trdgrb0 - 014ch, 014dh: grc0 trdgrc0 - 014eh, 014fh: grd0 trdgrd0 - 0155h: pocr1 -> trdpocr1 - 0156h, 0157h: trdcnt1 trd1 - 0158h, 0159h: gra1 trdgra1 - 015ah, 015bh: grb1 trdgrb1 - 015ch, 015dh: grc1 trdgrc1 - 015eh, 015fh: grd1 trdgrd1 22 5. electrical characteristics added 1.00 nov 15, 2006 all pages ?preliminary? and ?under development? deleted 2 table 1.1 functions and specifications for r8c/20 group revised. note1 deleted. 3 table 1.2 functions and specifications for r8c/21 group revised. note1 deleted. 5 table 1.3 product information for r8c/20 group; ?r5f2120ajfp (d)?, ?r5f2120cjfp (d)?, ?r5f2120akfp (d)?, ?r5f2120ckfp (d)?, and note added. figure 1.2 type number, memory size, and package of r8c/20 group; ?a: 96 kb? and ?c: 128 kb? added. 6 table 1.4 product information for r8c/21 group; ?R5F2121AJFP (d)?, ?r5f2121cjfp (d)?, ?r5f2121akfp (d)?, ?r5f2121ckfp (d)?, and note added. figure 1.3 type number, memory size, and package of r8c/21 group; ?a: 96 kb? and ?c: 128 kb? added. 13 figure 3.1 memory map of r8c/20 group revised. 14 figure 3.2 memory map of r8c/21 group revised. 15 table 4.1 sfr information (1) (1) ; note8; ?the csproini bit in the ofs register is set to 0.? ?the csproini bit in the ofs register is 0.? revised. 21 table 5.1 absolute maximum rati ngs; power dissipation revised. table 5.2 recommended operating conditions; system clock revised. 26 table 5.8 voltage monitor 1 reset circuit electrical characteristics table 5.8 power-on reset circuit, voltage monitor 1 reset circuit electrical characteristics (1) replaced. table 5.8 revised. note3 added. table 5.9 power-on rese t circuit electrical ch aracteristics deleted. figure 5.3 power-on re set circuit electrical characteristics revised. 27 table 5.10 high-speed on-chip oscillator circuit electrical characteristics table 5.9 high-speed on-c hip oscillator circuit electrical charac teristics revised. rev. date description page summary
a - 3 revision history r8c/20 group, r8c/21 group datasheet 1.00 nov 15, 2006 33 table 5.15 electrical characteristics (1) [vcc = 5 v] table 5.14 electrical characte ristics (1) [vcc = 5 v] revised. ram hold voltage, min.; ?1.8? ?2.0? corrected. 34 table 5.16 electrical characteristics (2) [vcc = 5 v] table 5.15 electrical characteristics (2) [vcc = 5 v] revised. wait mode revised. 37 table 5.21 electrical characteristics (3) [vcc = 3 v table 5.20 electrical characteristics (3) [vcc = 3 v] revised. ram hold voltage, min.;?1.8? ?2.0? corrected. 38 table 5.22 electrical characteristics (4) [vcc = 3 v] table 5.21 electrical characteristics (4) [vcc = 3 v] revised. wait mode revised. 2.00 aug 27, 2008 ? ?renesas technical update? reflected: tn-16c-a172a/e 5, 6 table 1.3, table 1.4 revised figure 1.2, figure 1.3; rom number ?xxx? added 13, 14 figure 3.1, figure 3.2; ?expanding area? deleted 21 table 5.2; note2 revised 23 table 5.4; note2 and note4 revised 24 table 5.5; note2 and note5 revised 25 table 5.6; ?td(vdet1-a)? added, note5 added table 5.7; ?td(vdet2-a)? and note2 revised, note5 added 26 table 5.8; ?trth? and note2 revised figure 5.3 revised rev. date description page summary all trademarks and registered trademarks are the property of thei r respective owners.
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